1. Field of the Invention
This invention relates generally to the field of semiconductor processing and, more particularly, to a method and apparatus for characterizing semiconductor device performance variations based on independent critical dimension measurements.
2. Description of the Related Art
Semiconductor integrated circuit devices are employed in numerous applications, including microprocessors. Generally, the performance of a semiconductor device is dependent on both the density and the speed of the devices formed therein. A common element of a semiconductor device that has a great impact on its performance is a transistor. Design features, such as gate length and channel length, are being steadily decreased in order to achieve higher package densities and to improve device performance. The rapid advance of field effect transistor design has affected a large variety of activities in the field of electronics in which the transistors are operated in a binary switching mode. In particular, complex digital circuits, such as microprocessors and the like, demand fast-switching transistors. Accordingly, the distance between the drain region and the source region of a field effect transistor, commonly referred to as the channel length or gate length dimension, has been reduced to accelerate the formation of a conductive channel between a source and a drain electrode as soon as a switching gate voltage is applied and, moreover, to reduce the electrical resistance of the channel.
A transistor structure has been created where the longitudinal dimension of the transistor, commonly referred to as the width dimension, extends up to 20 xcexcm, whereas the distance of the drain and source, i.e., the gate length, may be reduced down to 0.2 xcexcm or less. As the gate length of the channel has been reduced to obtain the desired switching characteristic of the source-drain line, the length of the gate electrode is also reduced. Since the gate electrode is typically contacted at one end of its structure, the electrical charges have to be transported along the entire width of the gate electrode, i.e., up to 20 xcexcm, to uniformly build up the transverse electric field that is necessary for forming the channel between the source and drain regions. Due to the small length of the gate electrode, which usually consists of a doped polycrystalline silicon, the electrical resistance of the gate electrode is relatively high, and it may cause high RC-delay time constants. Hence, the transverse electrical field necessary for fully opening the channel is delayed, thereby further deteriorating the switching time of the transistor line. As a consequence, the rise and fall times of the electrical signals are increased, and the operating frequency, i.e., the clock frequency, has to be selected so as to take into account the aforementioned signal performance.
In view of the foregoing, the control of the critical dimensions of the gate electrode is an increasingly important element of the fabrication process. If a gate electrode is formed overly large, its switching speed is compromised. On the other hand, if the gate electrode is formed too small, based on the design characteristics of the adjacent dielectric materials, the transistor will exhibit a higher leakage current, causing an excessive power usage and heat generation. Hence, its is important to control critical dimensions of a gate electrode such that the variation around a target gate electrode value is minimized.
One technique for reducing the gate electrode critical dimension variation is to perform post-etch metrology to determine the actual dimensions of the gate electrode after they are formed (i.e., typically by an anisotropic etching process). A scanning electron microscope is one tool suitable for gathering the metrology data. Based on the metrology information, the tools responsible for performing the previous steps in the fabrication process may be fine tuned to bring the actual dimensions closer to the target critical dimensions. For example, a photolithography stepper or an etch tool may be adjusted.
The metrology tools (e.g., scanning electron microscope) used to perform the critical dimension metrology are extremely sensitive. Accordingly, these tools are calibrated frequently, as much as several times per day. Even with such oversight, it is possible for the metrology tool to drift, thus resulting in a drift in the critical dimension measurements. This xe2x80x9cmetrology driftxe2x80x9d causes perceived variations in the critical dimensions of the gate electrode independent of the xe2x80x9cprocess driftxe2x80x9d caused by variations introduced by the previous process steps. Often, metrology drifts may be incorrectly characterized as process drifts, and the previous processing tools may be adjusted to attempt to correct the drift.
Typically, the performance of the device is not tested until a number of processing steps after the gate electrode has been formed (i.e., typically after the first metal layer is formed). It is only at this point that the success of the previous process adjustments is evident. Electrical tests such as effective gate length and drive current determine the performance of the device. Adjusting the process based on errant deviations caused by metrology drifts may actually increase the variation in the gate electrode critical dimensions. For example, the errant metrology tool may improperly indicate that the gate electrodes are too large. The process may be adjusted to further reduce the gate electrode length, resulting in the formation of gate electrodes that are actually too small. When the devices reach the point where they can be electrically tested, they may have excessive leakage and perform poorly, depending on the magnitude of the errant length reduction.
The present invention is directed to overcoming, or at least reducing the effects of, one or more of the problems set forth above.
One aspect of the present invention is seen in a method for characterizing semiconductor device performance variations includes processing a wafer in a processing line to form a feature on the wafer; measuring a physical critical dimension of the feature in a first metrology tool to generate a first critical dimension measurement; measuring the physical critical dimension of the feature in a second metrology tool to generate a second critical dimension measurement independent of the first critical dimension measurement; determining an effective critical dimension of the feature in a third metrology tool to generate a third critical dimension measurement; and comparing the first, second, and third critical dimension measurements to identify a metrology drift in one of the first and second metrology tools.
Another aspect of the present invention is seen in a system for characterizing semiconductor device performance variations. The system includes a processing line, first, second, and third metrology tools, and a process controller. The processing line is adapted to process a wafer to form a feature on the wafer. The first metrology tool is adapted to measure a physical critical dimension of the feature to generate a first critical dimension measurement. The second metrology tool is adapted to measure the physical critical dimension of the feature to generate a second critical dimension measurement independent of the first critical dimension measurement. The third metrology tool adapted to determine an effective critical dimension of the feature to generate a third critical dimension measurement. The process controller is adapted to compare the first, second, and third critical dimension measurements to identify a metrology drift in one of the first and second metrology tools.